In the design of phase locked loops (PLLs), a critical component is the phase detector since it has a number of factors that limit performance of the PLL. In digital PLL's the principal limitations become worse when the time domain is quantized.
A conventional analog PLL typically is constructed as shown in FIG. 1. A phase detector is used to determine the difference between two phase signals, one being the feedback signal. The output of the phase detector is fed to the filter section, which may for instance be P type only (Proportional) but typically will be PI type (Proportional Integral), yielding a so-called type II PLL. The filter feeds a controlled oscillator (which in FIG. 1 is a Voltage or Current Controlled Oscillator). The generated frequency is divided and fed back to the input.
The analysis of such a Phase Locked Loop or PLL is typically done using Black's formula to analyze bandwidth of the closed loop, overshoot, peaking and the like.
Analog PLL's have quite a few limitations for which digital PLL's have much better performance. This results from the different nature of digital PLL's, i.e. PLL's where the phase signal is sampled and then used to eventually control a Digitally Controlled Oscillator or DCO. The advantages that digital PLL's are:                a) Simple and accurate holdover. If there is no reference signal, a digital PLL can use its current or some historic DCO setting to sustain the same output frequency. A digital PLL will typically rely on stability of its clock signal to achieve this, which mostly will come from a crystal oscillator. Analog PLL's typically have much less stable elements in their structure to rely upon.        b) A digital PLL will have no difficulty providing extreme bandwidths like 10 mHz, which is very difficult for analog PLL's. Again a digital PLL relies on the stability of its clock.        c) A digital PLL can handle extremely low input frequencies like 1 Hz. An analog PLL will introduce a lot of noise at the phase detector, charge pump and the like, as all the noise from the analog elements will be folded back into a small frequency band.        
A typical digital PLL looks a lot like an analog PLL, as shown in FIG. 2. If we accept that digital processing can be designed such that errors, such as rounding and cut-off errors, can always be limited to low enough levels, the following remaining error sources exist:                a) The system clock (stability, noise) will be part of the remaining error terms.        b) The input sampling limits accuracy.        c) The output frequency synthesis limits accuracy, both by being in the feedback loop as in direct output contribution.        
Various prior art circuits are described in U.S. Pat. Nos. 5,602,884; 7,006,590; and 5,905,388.